In semiconductor device manufacturing field, efforts of scaling devices such as transistors, and particularly field-effect-transistor (FET) devices, have recently been focused on improving stress engineering to the devices. For example, when a p-type FET (pFET) device is manufactured, silicon-germanium (SiGe) may be embedded (eSiGe) in source and drain regions of the pFET device as stressors, which have successfully demonstrated their effectiveness in improving performance of the pFET device. However it is noted that, while this eSiGe process or technology is considered as useful in improving performance of pFET devices, it is generally not applicable to other types of devices such as, for example, n-type FET (nFET) devices which may be manufactured together with pFET devices.
FIGS. 8-11 illustrate a conventional method or process of manufacturing pFET and nFET together, with eSiGe technology being applied only to the pFET for performance enhancement. In particular, FIG. 8 illustrates a step of forming pFET 310 and nFET 410 on a common substrate, which may include substrates 301 and 401 illustrated separately in FIG. 8 for description purpose. pFET 310 may include gate 303, adjacent oxide spacers 304, and source/drain regions 302 wherein SiGe may be embedded (eSiGe). Conventionally, eSiGe 302 in the source/drain regions of pFET 310 is formed through a disposable spacer process, which generally results in no oxide spacers being left on top of eSiGe 302. On the other hand, nFET 410, which may be manufactured together with pFET 310, may have an oxide spacer 404 covering not only gate 403 but also source/drain regions 402 of nFET 410, as illustrated on the right side of FIG. 8.
Following forming eSiGe 302, conventionally, a layer of oxide material (306, 406) may be deposited on top of pFET 310 and nFET 410, as illustrated in FIG. 9, to form offset spacers. After the deposition, the oxide layer (306, 406) may be subjected to a directional etching process (309, 409) as illustrated in FIG. 10, such as a reactive-ion-etching (RIE) process. The directional etching process forms offset spacers 307 and 407, as illustrated in FIG. 11, and expose source and drain regions of pFET 310 and nFET 410 for further treatment. For example, with regard to nFET 410, oxide layer 406 may be removed first and oxide spacer 404 may be removed next from the top of source/drain regions of nFET 410. However, during the removal of spacer 404, SiGe embedded in the source/drain regions of pFET 310 (eSiGe 302), because the top thereof is not covered by oxide spacer 304, may be subjected to or exposed to the same processing conditions as those for removing spacer 404. As a result, the directional etching process may cause erosion 308, or damage, or over-etch, as illustrated in FIG. 11, of eSiGe 302 of pFET 310. This ultimately may cause performance degradation in the final finished pFET product.
Therefore, there exists in the art a need to develop new and/or improved method and/or process that may be applied in forming field-effect-transistors, and in particular in forming pFET and nFET together, with pFET being enhanced by embedded SiGe process with reduced or minimal eSiGe erosion during the process of manufacturing thereof.